1. Field of the Invention
The present invention relates generaly to a video signal control circuit and, more particularly, is directed to a video signal control circuit such as a frame synchronizer and the like for use with a so-called down converter which is used to convert a video signal having a number of scanning lines to a video signal having scanning lines according to a standard television system.
2. Description of the Prior Art
The number of scanning lines of a video signal to reproduce, for example, a high definition televison picture is about twice the number of a video signal according to the existing standard television system. When the video signal having a large number of scanning lines (e.g., video signal having 1125 horizontal scanning lines) is converted to a video signal (e.g., video signal having 625 horizontal scanning lines according to the
system) having scanning lines according to the existing standard television system, it is general that a so-called down converter is used for converting the number of horizontal scanning lines.
The down converter is provided with the frame synchronizer, in which the above mentioned input video signal is written in a frame memory and a data stored in the frame memory is read out thereform in synchronism with an internal reference signal provided in the frame synchronizer whereby the number of horizontal scanning lines is reduced and an asynchronous input video signal is snychronized with the internal reference signal and then generated.
Since the input video signal is generaly not synchronized with the internal reference signal as described above, if in the writing and/or reading process in and/or from the frame memory the frame memory is capable of storing an input video signal of about two frame periods, the frame memory has to carry out the reading after the writing was ended. As a result, the overlapping of the writing operation and the reading operation will take place about once at each day. In other words, if this overlapping state is left as it is, the timing relation between the writing operation and the reading operation will become closer. Thus, such a state that the writing and reading state, in which the writing and reading are impossible (overlapping state), will occur ultimately.
The reason for this is that the accuracy of a reference signal generator for an input video signal (in many cases, a crystal oscillator is used as the reference generator), accordingly, the accuracy of the crystal oscillator is different from that of a crystal osciallator that is provided in the internal reference signal generator.
In the prior art, when the overlapping of the writing operation and the reading operation occurs, for example, when the writing operation precedes the reading operation too much, a writing frame address (or field address) is stoped during one frame period to thereby delete a data of one picture amount. While, when on the other hand the reading operation precedes the writing operation too much, the data of the same picture is read out again from the overlapping frame to thereby prevent the skipping of the memory.
For example, if the write timing delays as to the read timing, as shown in FIGS. 1A and 1B, the write timing (shown by a write address data, WADRS, in the illustrated example) approaches gradually the read timing (shown by R.ADRS) and at last, the write timing and the read timing coincide with each other. For this reason, if the write timing tends to be delayed as mentioned above, when both the write timing and the read timing approach to each other with a minimum approaching distance in which the data can not be read, that is, with a minimum timing distance Ta therebetween, a read address generator is controlled to be placed in the re-reading mode under which the same frame data is read out again.
Conversely, if the write timing precedes the read timing, the write timing approaches gradually the read timing as shown in FIGS. 1C and 1D so that the write timing and the read timing become coincident with each other ultimately. For this reason, if the writing timing tends to precede the read timing as described above, when both the write timing and the read timing approach to each other with a minimum timing distance Tb in which the data can not be written, the write address generator is controlled to be placed in the re-writing mode under which the same frame data is written once again.
In order to control the write mode and the read mode, frame pulses FR and FW (shown in FIGS. 2A and 2B) of 2 frame periods are formed from the write address data and the read address data, respectively. On the basis of a point at which the write frame pulse FW changes, there are respectively formed pulses Ra and Rb shown in FIGS. 2E and 2F. One pulse Ra is used to detect the mode in which the data is read out again so that its pulse width or pulse duration is set to be the distance Ta in which the data can not be read out as described above. Similarly, another pulse Rb is used to detect the mode in which the data is written in again. The pulse duration of the pulse Rb is set to be the distance Tb.
By the way, in the prior art, if the overlapping relation between the write timing and the read timing occurs within the data writing disabled spacing Ta and the data reading disabled spacing Tb, the writing and/or reading address generator is controlled immediately so as to stop the writing mode or to execute the re-reading mode. As a result, this overlapping state frequently takes place in the necessary picture. At that time, if the address generator is controlled so as to delete the data or one frame period or to read the same picture data of one frame period again, an unnatural motion occurs in the animation except for the still picture.